The present invention relates to a data processing machine suitable for high-speed processing, and more particularly to a data processing machine fit for processing programs which must be processed through repeated executions of a certain operation flow.
There has been heretofore adopted a well known control flow mode in microprocessors. A basic process of this mode is such that a necessary instruction is fetched by accessing a memory, the fetched instruction is decoded to read out data and execute the processing specified by the instruction, and the result is stored in the memory. Such a process is sequentially repeated so as to process a set of program instructions. In order to use the processor of this kind in a field (e.g., image processing or voice processing) which requires high-speed processing, there have been attempts in the past to improve the operating speed of semiconductor devices used for the processor or to increase the number of bits treated in the processor at the same time. In the present situation, however, the former is limited due to difficulties in the semiconductor manufacturing technology and the latter leads to an increase in the size of the device and system and has a limit from the view point of economy.
Under the background as mentioned above, a pipe line mode has been proposed as an architecture adaptable to high-speed processing. This mode is based on parallel processing of data and is to control the respective operation flows (e.g., addition processing, subtraction processing, multiplication processing or division processing) for processing of programs in parallel. A processor system employing the pipe line mode is so structured that a plurality of arithmetic circuits each having a fixed single function, such as an adder or multiplier, are connected to each other in a ring form with a pipe line bus. This system is suitable for high-speed processing in that a plurality of operation flows can be executed in parallel. It is necessary, however, to select the kind of arithmetic circuits to be used and determine the sequence of the selected arithmetic circuits optimum for the given processing. Therefore, the operation system thus structured can produce an effect of the pipe line mode for the given processing, but has a defect that the performance is significantly reduced for other types of processing. Such reduction in the performance can be compensated to some degree by independently preparing the operation systems in accordance with the respective processings, but the kinds of required arithmetic circuits are increased and the system structure is enlarged, thus resulting in a great increase in cost.
Furthermore, computing time in each pipe line, that is, a period of time necessary for data to be input to the pipe line and then output therefrom, is fixed and the individual pipe lines have different computing times from one another. As a result, in the case where a plurality of processors of the pipe line mode are used to constitute a so-called multiprocessor, timing control of data transfer between the processors becomes very complicated. In addition, according to the conventional pipe line mode processor, it is difficult to cause processing to be looped within a pipe. Stated differently, processing can not be executed repeatedly within a single pipe line, so that such processing has required intricate software control and a prolonged processing time.
Meanwhile, in fields requiring high-speed processing (e.g., image processing adapted to process images from satellites or of X-ray photographs by a man-machine system), a large amount of data up to about 6 million pixels for each image has to be processed in a short period of time. For instance, to process one image in 3 seconds, the image has to be processed at a speed of 500 ns per 1 pixel. It is required, therefore, that the processor itself has a function to permit high-speed processing and that data transfer between the processor and the memory can be performed at a high speed. Particularly, the latter is a major problem for the conventional microprocessor in which the memory is accessed by using a program counter. As mentioned above, such a prior microprocessor is operated in the control flow mode where the program counter is employed as an address specifying means to fetch instructions from the memory and the fetched instructions are decoded so as to process data. Consequently, such a microprocessor is not suitable for high-speed processing because of the increased number of memory accesses.
To the contrary, a data flow mode in which data is caused to flow through a bus, a certain arithmetic circuit takes out the data and the result is fed to the next arithmetic circuit through the bus, has a reduced number of memory accesses and hence is fit for high-speed processing. This mode is characterized in that predetermined arithmetic processings are carried out along the bus, so that data is transferred while being treated sequentially and the final result is obtained at the end of the bus. In the data flow mode, however, it is difficult to control a flow of data and make coupling with the prior microprocessor. Therefore, the operation results do not meet expectations in repetitive operations, parallel processing or composite processing using a common bus. In other words, the data flow mode has a disadvantage such that it is not useful in the art of image processing including a number of those processings which do not require such high speed.